Integrated circuit memory devices are widely used in consumer and commercial electronics. As is well known to those having skill in the art, integrated circuit memory devices generally include a memory cell array and peripheral circuits for reading data from, writing data to, and controlling the memory cell array.
As the size of the memory cell array continues to increase, it may become increasingly difficult to test the memory cell array. In particular, in order to test the memory cell array, a large number of test patterns may be provided to the memory cell array, and the response of the memory cell array to the test patterns may be monitored. This testing may be time-consuming and may use all of the input/output pins of the integrated circuit memory device, which may thereby limit the number of memory devices that may be tested simultaneously. Accordingly, it is known to provide a memory test pattern and control circuit in the integrated circuit memory device itself, in order to provide Built-In Self Test (BIST). More specifically, a BIST unit in the integrated circuit memory device may include a memory test pattern that is used to perform the BIST.
It is also generally known to provide stress testing of the memory cell array by applying a stress voltage that is larger than the internal supply voltage of the integrated circuit memory device, to the memory, while performing the BIST on the memory cell array. However, it may be difficult to supply the stress voltage to the memory cell array while performing the BIST on the memory cell array. Moreover, application of the stress voltage may damage the integrated circuit memory device. Finally, separate burn-in testers may be needed to test the memory using a stress voltage.